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| TN2425TG Datasheet, PDF (1/5 Pages) Supertex, Inc – Low Threshold Dual N-Channel Enhancement-Mode | |||
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TN2425TG
Low Threshold Dual N-Channel Enhancement-Mode
Vertical DMOS FET
Features
⺠Dual N-channel device
⺠Low threshold â 2.0V max.
⺠High input impedance
⺠Low input capacitance â 200pF
⺠Fast switching speeds
⺠Low caps ON resistance
⺠Free from secondary breakdown
⺠Low input and output leakage
Applications
⺠Logic level interfaces â ideal for TTL and CMOS
⺠Solid state relays
⺠Medical ultrasound pulsers
⺠Analog switches
⺠General purpose line drivers
⺠Telecom switches
General Description
The Supertex TN2425TG is a dual low threshold
enhancement mode (normally off) transistor utilizing
a vertical DMOS structure and Supertexâs well proven
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors, with the high input impedance and
positive temperature coefï¬cient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertexâs vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
Package Option
8-Lead SOIC (Narrow Body)
TN2425TG
TN2425TG
BVDSS/BVDGS
250V
RDS(ON) (max)
3.5Ω
VGS(th) (max)
2.0V
ID(ON) (min)
1.8A
Absolute Maximum Ratings
Parameter
Value
Drain to source voltage
Drain to gate voltage
Gate to source voltage
Thermal resistance,
Junction to drain lead
Operating and storage temperature
BVDSS
BVDGS
±20V
50°C/W
-55°C to +150°C
Soldering temperature1
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Note 1. Distance of 1.6mm from case for 10 seconds.
Pin Conï¬guration
S1 1
G1 2
S2 3
G2 4
8-Lead SOIC
(top view)
8 D1
7 D1
6 D2
5 D2
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