TN0602 Datasheet, PDF (1/4 Pages) Supertex, Inc – N-Channel Enhancement-Mode Vertical DMOS FETs

TN0602
TN0604
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV_DSS /
BV_DGS
20V
R_DS(ON)
(max)
0.75Ω
I_D(ON)
(min)
4.0A
V_GS(th)
(max)
1.6V
Order Number / Package
TO-92
SOW-20*
—
—
40V
0.75Ω
4.0A
1.6V
TN0604N3
—
40V
1.0Ω
4.0A
1.6V
—
TN0604WG
7
* Same as SO-20 with 300 mil wide body.
Features
Low threshold — 1.6V max.
High input impedance
Low input capacitance — 140pF typical
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
* Distance of 1.6 mm from case for 10 seconds.
BV_DSS
BV_DGS
± 20V
-55°C to +150°C
300°C
SGD
TO-92
SOW-20
Notes:
1. See Package Outline section for dimensions.
2. See Array section for quad pinouts.
7-47