TN0110_13 Datasheet, PDF (1/5 Pages) Supertex, Inc – N-Channel Enhancement-Mode Vertical DMOS FET

Supertex inc.
TN0110
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
►► Low threshold - 2.0V max.
►► High input impedance
►► Low input capacitance - 50pF typical
►► Fast switching speeds
►► Low on-resistance
►► Free from secondary breakdown
►► Low input and output leakage
Applications
►► Logic level interfaces – ideal for TTL and CMOS
►► Solid state relays
►► Battery operated systems
►► Photo voltaic drives
►► Analog switches
►► General purpose line drivers
►► Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
TN0110N3-G
TO-92
TN0110N3-G P002
Packing
1000/Bag
Product Summary
BV_DSS/BV_DGS
R_DS(ON)
(max)
100V
3.0Ω
I_D(ON)
(min)
2.0A
V_GS(th)
(max)
2.0V
TN0110N3-G P003
TN0110N3-G P005 TO-92
TN0110N3-G P013
TN0110N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
2000/Reel
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BV_DSS
BV_DGS
±20V
Operating and storage temperature
-55^OC to +150^OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Typical Thermal Resistance
Pin Configuration
SOURCE
DRAIN
GATE
TO-92
Product Marking
SiTN _{YY = Year Sealed}
0 1 1 0 _{WW = Week Sealed}
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
Package
TO-92
θ_ja
132^OC/W
Doc.# DSFP-TN0110
C080813
Supertex inc.
www.supertex.com