TN0106 Datasheet, PDF (1/4 Pages) Supertex, Inc – N-Channel Enhancement-Mode Vertical DMOS FETs

TN0106
TN0110
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV_DSS /
BV_DGS
60V
R_DS(ON)
(max)
3.0Ω
100V
3.0Ω
† _{MIL visual screening available}
Features
I_D(ON)
(min)
2A
2A
s Low threshold — 2.0V max.
s High input impedance
s Low input capacitance — 50pF typical
s Fast switching speeds
s Low on resistance
s Free from secondary breakdown
s Low input and output leakage
s Complementary N- and P-channel devices
V_GS(th)
(max)
2.0V
2.0V
Applications
s Logic level interfaces – ideal for TTL and CMOS
s Solid state relays
s Battery operated systems
s Photo voltaic drives
s Analog switches
s General purpose line drivers
s Telecom switches
Order Number / Package
TO-92
Die^†
TN0106N3
—
TN0110N3
TN0110ND
7
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
* Distance of 1.6 mm from case for 10 seconds.
BV_DSS
BV_DGS
± 20V
-55°C to +150°C
300°C
SGD
TO-92
Note: See Package Outline section for dimensions.
7-35