TC2320_08 Datasheet, PDF (1/4 Pages) Supertex, Inc – N- and P-Channel Enhancement-Mode Dual MOSFET

TC2320
N- and P-Channel Enhancement-Mode Dual MOSFET
Features
► Low threshold
► Low on-resistance
► Low input capacitance
► Fast switching speeds
► Freedom from secondary breakdown
► Low input and output leakage
► Independent, electrically isolated N- and P-channels
Applications
► Medical ultrasound transmitters
► High voltage pulsers
► Amplifiers
► Buffers
► Piezoelectric transducer drivers
► General purpose line drivers
► Logic level interface
General Description
The Supertex TC2320 consists of a high voltage, low
threshold N- and P-channel MOSFET in an 8-Lead SOIC
package. This low threshold enhancement-mode (normally-
off) transistor utilizes an advanced vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
8-Lead SOIC (Narrow Body)
4.90x3.90mm body,
1.75mm height (max)
1.27mm pitch
TC2320
TC2320TG-G
-G indicates package is RoHS compliant (‘Green’)
BV_DSS/BV_DGS
(V)
N-Channel
200
P-Channel
-200
R_DS(ON)
(max)
(Ω)
N-Channel
P-Channel
7.0
12
Pin Configuration
DP
DP
DN
DN
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BV_DSS
BV_DGS
±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature*
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
GP
SP
GN
SN
8-Lead SOIC (TG)
Product Marking
YYWW
C2320
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC (TG)
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: [phone] ● www.supertex.com