HV7224 Datasheet, PDF (1/7 Pages) Supertex, Inc – 40-Channel Symmetric Row Driver

HV7224
40-Channel Symmetric Row Driver
Ordering Information
Device
80-Lead
Ceramic Gullwing
Package Options
64-Lead 3-Sided
Plastic Gullwing
Die in waffle pack
HV7224
HV7224DG
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
HV7224PG
HV7224X
80-Lead
Ceramic Gullwing
(MIL-STD-883 Processed*)
RBHV7224DG
Features
❏ Processed with HVCMOS^® technology
❏ Symmetric row drive (reduces latent imaging
in ACTFEL displays)
❏ Output voltage up to 240V
❏ Low-power level shifting
❏ Source/Sink current 70mA (min.)
❏ Shift Register Speed 3MHz
❏ Pin-programmable shift direction (DIR, SHIFT)
❏ Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, V_DD1
-0.5V to +7V
Supply voltage, V_PP
-0.5V to +260V
Logic input levels
-0.5V to V_DD +0.5V
Continuous total power dissipation ² Plastic
Ceramic
1200mW
1900mW
Operating temperature range
Plastic -40°C to +85°C
Ceramic -55°C to +125°C
Storage temperature range
-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
260°C
Notes:
1. All voltages are referenced to GND.
2. For operation above 25°C ambient derate linearly to maximum operating tem-
perature at 20mW/°C for plastic and at 19mW/°C for ceramic.
General Description
The HV72 is a low-voltage serial to high-voltage parallel convert-
ers with push-pull outputs. It is especially suitable for use as a
symmetric row driver in AC thin-film electroluminescent (ACTFEL)
displays.
When the data reset pin (DR_IO) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR can be
IO
triggered at any time. The DIR and SHIFT pins control the
direction of data shift through the device. When DIR is at logic
high, DR is the input and DR is the output. When DIR is
IOA
IOB
grounded, DR_IOB is the input and the DR_IOA is the output. See the
Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to V_PP if
POL is high, or to GND if POL is low. All outputs will be in High-
Z state if OE is at logic high. Data output buffers are provided for
cascading devices.
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex prod1ucts, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.