HV6810_07 Datasheet, PDF (1/8 Pages) Supertex, Inc – 10-Channel Serial-Input Latched Display Driver

HV6810
10-Channel Serial-Input Latched Display Driver
Features
General Description
► High output voltage 80V
► High speed 5MHz @ 5.0V_DD
► Low power I_BB ≤ 0.1mA (all high)
► Active pull down 100µA min
► Output source current 100mA at 60V V_PP
► Each device drives 10 lines
► High-speed serially-shifted data input
► 5.0V CMOS-compatible inputs
► Latches on all driver outputs
► Pin-compatible replacement for UCN5810A and
TL4810A, TL4810B
Applications
► High speed dot matrix print head driver
► VFD (vacuum fluorescent display) driver
The HV6810 is a monolithic integrated circuit designed
to drive a dot matrix or segmented vacuum fluorescent
display (VFD). These devices feature a serial data output to
cascade additional devices for large displays.
A 10-bit data word is serially loaded into the shift register
on the positive-going transition of the clock. Parallel data
is transferred to the output buffers through a 10-bit D-type
latch while the latch enable input is high, and is latched
when the latch enable is low. When the blanking input is
high, all of the outputs are low.
Outputs are structures formed by double-diffused MOS
(DMOS) transistors with output voltage ratings of 80V and
25mA source-current capability. All inputs are compatible
with CMOS levels.
Ordering Information
Pin Configurations
1
20
Package Options
Device
20-J Lead PLCC
20-Lead SOW
HV6810
HV6810PJ-G
HV6810WG-G
20
-G indicates package is RoHS compliant (‘Green’)
1
Absolute Maximum Ratings
Parameter
Value
Logic
supply
voltage,
V (1)
DD
Driver
supply
voltage,
V (1)
BB
Output voltage⁽¹⁾
7.5V
90V
90V
Input voltage⁽¹⁾
Continuous total power dissipation
at 25^OC free-air temperature
20-J Lead PLCC (PJ)
20-Lead SOW (WG)
-0.3V to V_DD+ 0.3V
1000mW⁽²⁾
1000mW⁽²⁾
Operating temperature range
-45°C +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Notes:
(1) All voltages are referenced to V_SS.
(2) For operation above 25^OC ambient derate linearly to 85^OC at 16.7mW/^OC.
20-J Lead PLCC (PJ)
(top view)
20-Lead SOW (WG)
(top view)
Product Marking
Top Marking
YYWW
HV6810PJ
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
20-J Lead PLCC (PJ)
Top Marking
YYWW
HV6810WG
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
20-Lead SOW (WG)