HV507 Datasheet, PDF (1/5 Pages) Supertex, Inc – 300V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs

HV507
300V, 64-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Ordering Information
Device
HV507
Recommended Operating
V_PP Max*
300V
* Please consult factory for higher voltage operation.
Package Options
80-Lead Plastic
Gullwing
Die
HV507PG
HV507X
Features
❏ HVCMOS^® technology
❏ Operating output voltage of 300V
❏ Low power level shifting from 5V to 300V
❏ Shift register speed 8MHz @ V_DD = 5V
❏ 64 latched data outputs
❏ Output polarity and blanking
❏ CMOS compatible inputs
❏ Forward and reverse shifting options
Absolute Maximum Ratings¹
Supply voltage, V_DD
Supply voltage, V_PP
Logic input levels
Ground current³
-0.5V to +6V
V_DD to 320V
-0.5V to V_DD +0.5V
0.5A
High voltage supply current²
0.5A
Continuous total power dissipation³
1200mW
Operating temperature range
0°C to +70°C
Storage temperature range
-65°C to +150°C
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 70°C at 26.7mW/°C.
General Description
The HV507 is a low voltage serial to high voltage parallel con-
verter with 64 high voltage push-pull outputs. This device has
been designed for use as a printer driver for electrostatic applica-
tions. It can also be used in any application requiring multiple high
voltage outputs, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D_IOA is Data In and D_IOB is Data Out;
data is shifted from HV_OUT64 to HV_OUT1. When DIR is at logic high,
D_IOB is Data In and D_IOA is Data Out: data is then shifted from
HV_OUT1 to HV_OUT64. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE, BL, or the POL inputs. Transfer of data from
the shift register to the latch occurs when the LE is high. The data
in the latch is stored during LE transition from high to low.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex prod¹ucts, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.