HV506 Datasheet, PDF (1/9 Pages) Supertex, Inc – 275V 40-Channel Row Driver with SCR Outputs

HV506
275V 40-Channel Row Driver with SCR Outputs
Preliminary
Ordering Information
Device
HV506
80-Lead
Ceramic Gullwing
HV506DG
Package Options
64-Lead 3-Sided
Plastic Gullwing
HV506PG
Die
HV506X
Features
❏ Processed with HVDI^ technology
❏ Symmetric row drive
❏ Output voltage up to 275V
❏ Source/Sink current 300mA (min.)
❏ Shift Register Speed 3MHz
❏ Pin-programmable shift direction (DIR)
❏ Hi-Rel processing available
Absolute Maximum Ratings
Logic supply voltage, LV_DD1
-0.5V to +15V
Output supply voltage, V_DD1
-0.5V to +15V
Substrate bias voltage, V_sub
See Note 3
Output voltage, HV_OUT
±300V
Logic input levels
-0.5V to V_DD +0.5V
Continuous total power dissipation² Ceramic
1900mW
Plastic
1200mW
Operating temperature range
Plastic -40°C to +85°C
Ceramic -55°C to +125°C
Storage temperature range
-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
260°C
Notes:
1. All voltages are referenced to V .
SS
2. For operation above 25°C ambient derate linearly to maximum operating
temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic.
3. V_sub must be the most positive with respect to V_SS.
General Description
The HV506 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. It is especially suitable for use as
a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DR ) is at logic high, it will reset all the
IO
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR can be
IO
triggered at any time. The DIR pin controls the direction of data
through the device. When DIR is at logic high, DR_IOA is the input
and DR is the output. When DIR is grounded, DR is the input
IOB
IOB
and the DR_IOA is the output. See the Output Sequence Operation
Table for output sequence. The POL and OE pins perform the
polarity select and output enable function respectively. Data is
clocked through the shift register loaded on the low to high
transition of the clock. A logic high in the shift register will cause
the other corresponding output to swing to V_DD if POL is high, or
to V if POL is low. All other outputs will be in the High-Z state.
SS
If OE is at logic high all outputs will be in the High-Z state. An
output in the High-Z state may block up to 275V above V_SS or
275V below V . The D /D pins are for the positive/negative
DD
PN
discharge of the high voltage output HV_OUT. Data output buffers
are provided for cascading devices.
LV requires low current for the HV506 logic section. V
DD
DD
requires high current for the output section . Typically these two
pins are at the same potential. The same current and potential
conditions apply to the LV , logic, and V , output pins. V must
SS
SS
sub
always be equal or greater than the most positive supply.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and s1pecifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.