HV3527 Datasheet, PDF (1/5 Pages) Supertex, Inc – 275V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs

HV3527
275V, 64-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Ordering Information
Package Options
Device
HV3527
Recommended
Operating
V_PP Max
275V
80-Lead
Quad Plastic
Gullwing
HV3527PG
Features
■ HVCMOS^® technology
■ Output voltages up to 275V
■ Low power level shifting
■ Shift register speed 6MHz @ V_DD = 5V
■ Latched data outputs
■ Output polarity and blanking
■ CMOS compatible inputs
■ Forward and reverse shifting options
Absolute Maximum Ratings¹
Supply voltage, V_DD
Supply voltage, V_PP
Logic input levels
Ground current²
High voltage supply current²
Continuous total power dissipation³
-0.5V to +6V
V_DD to 300V
-0.5V to V_DD +0.5V
1.5A
1.3A
1200mW
Operating temperature range
0°C to +70°C
Storage temperature range
-65°C to +150°C
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 85°C at 15mW/°C.
General Description
(Not recommended for new designs. Please use HV507 with
improved performance.)
The HV35 is a low voltage serial to high voltage parallel converter
with push-pull outputs. This device has been designed for use as
a printer driver for electrostatic applications. It can also be used
in any application requiring multiple output high voltage, low
current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D_IOA is Data-In and D_IOB is Data-Out;
data is shifted from HV_OUT64 to HV_OUT1. When DIR is at logic high,
D_IOB is Data-In and D_IOA is Data-Out: data is then shifted from
HV_OUT1 to HV_OUT64. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE (latch enable) is high. The data in the latch is
stored during LE transition from high to low.
A bias pin is used to ensure that the device operates at full V_PP
voltage.
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