SMD1103 Datasheet, PDF (6/14 Pages) Summit Microelectronics, Inc. – 10-Bit Data Acquisition System for Autonomous Environmental Monitoring

SMD1102 / 1103 / 1113
DB7 DB6 DB5 DB4 DB0
Device Type Identifier R/M
Function
Enable auto-monitor
A2 A1 A0
0
or write EEPROM
limit register (E/C
or or or 1
state)
Read A/D con-
1* 0* 0*
1
version or EEPROM
limit register (E/C
state)
2033 Table01C
* Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113.
Table 1C. Address Byte — Read/Monitor
Single Channel Conversions
This command sequence is composed of: the Device
Type Identifier, followed by the E/C bit set to zero, then
the channel select bits set to the desired value, and the
R/M bit set to logic one. After the R/M bit is clocked in the
host releases the SDA line and monitors the SDA line for
an acknowledge bit (ACK) from the SMD1102/1103/1113.
The device will drive the SDA line low indicating it received
the command and that it has initiated the acquisition and
conversion on the selected channel. The clock source for
the acquisition and conversion is an internal clock. After
the ACK the SMD1102/1103/1113 will output four dummy
zeros on SDA followed by an echo of the channel’s 2
address bits. The remaining bits in this first byte are the
two MSBs of the conversion. Refer to Figure 2 for a
detailed illustration of this sequence, and for that of
retrieving the remaining conversion byte. The host can
issue a stop condition after retrieving the conversion data
and place the SMD1102/1103/1113 in a low power
standby mode.
Successive Single Channel Conversions
If the host does not issue a stop command after receiving
the last bit of the previous conversion, but instead issues
an ACK and continues clocking, then the SMD1102/1103/
1113 will begin another acquisition and conversion pro-
cess on the same channel.
Auto-Increment
In the auto-increment mode, the DAS starts a conversion
and then automatically advances to the next channel. The
auto-increment mode always starts at channel 0 and
switches the channel input in the sequence 0, 1, 2, 0, 1,
2, etc. after each successive conversion. The SMD1102,
SMD1103, and SMD1113 independently repeat this pro-
cess so long as the host continues clocking the device,
supplies ACK bits at the appropriate clock interval, and
issues no stop conditions. Refer to Figure 4 for a detailed
illustration of the sequence.
Programming the Limit Registers
Programming the nonvolatile limit registers of the
SMD1102/1103/1113 for use with the auto-monitor func-
tion is straightforward. Associated with each channel is
an 11-bit lower limit register and an 11-bit upper limit
register. Ten bits correspond to the 10-bit data, and the
MSB represents the monitor option bit. The monitor option
bits of the upper and lower limit combine to define the alert
region for each channel (described more fully in the
section labeled Alert Conditions). Each limit register
must be programmed separately with a three byte com-
mand sequence. To program the limit register the host
first issues a start condition, followed by the device type
identifier, the EEPROM/Conversion (E/C) bit (set to one),
the channel select bits, and the Read/Monitor bit (set to
zero). The second byte consists of four zeroes followed
by the limit select bit (zero = lower limit, one = upper limit),
the monitor option bit, and the two most significant bits of
the limit data. The third byte consists of the remaining
eight bits of limit data. After receiving a stop condition,
the SMD1102/1103/1113 initiates its internal program
sequence. Refer to Figure 5 for details. Six such
sequences are required to set the upper and lower limits
for all three channels. However, once programmed the
data remains stored in EEPROM until reprogrammed.
For example, when a device has both VDD and VREF at
5.00V, and an alert must be generated if the voltage on any
channel is ≤2.00V or >3.00V, then the monitor option bits
are set to 10BIN, the upper limit is set to 266HEX, and the
lower limit is set to 199HEX.
Reading the Limit Registers
The timing diagram for reading the limit register data of a
particular channel is shown in Figure 6. The five byte
sequence commences with a start condition, followed by
the device type identifier, the EEPROM/Conversion bit
(set to one), the channel select bits, and the Read/Monitor
bit (set to one). After acknowledging the slave byte the
device outputs a one, followed by an echo of the channel
select bits, a zero, another zero (representing the lower
limit data), the monitor option bit and the two most
significant bits of the limit data. The third byte consists
of the remaining eight bits of the lower limit data. The
fourth byte of the output sequence is the same as the
second byte except the fifth bit is a one (to indicate upper
6
2033 8.1 10/04/01
SUMMIT MICROELECTRONICS, Inc.