S24042 Datasheet, PDF (6/14 Pages) Summit Microelectronics, Inc. – Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs

S24042/S24043
Acknowledge Polling
When the S24042/43 is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 6).
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to “1.” There are four different read
options:
1. Current Address Byte Read
2. Random Address Byte Read
3. Current Address Sequential Read
4. Random Address Sequential Read
Internal WRITE Cycle
In Progress;
Begin ACK Polling
Issue Start
Issue Slave
Address and
R/W = 0
Issue Stop
ACK
No
Returned?
Yes (Internal WRITE Cycle is completed)
Next
operation a ^No
WRITE?
Yes
Issue Byte
Address
Issue Stop
Current Address Byte Read
The S24042/43 contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S24042/43 receives the slave address field with the R/W
bit set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1.
The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the S24042/43 discontinues data transmission. See Fig-
ure 7 for the address acknowledge and data transfer
sequence.
Proceed with
WRITE
Await Next
Command
2011 ILL9 1.0
FIGURE 6. ACKNOWLEDGE POLLING
2011 2.1 8/2/00
SDA Bus Activity 1
A
X XX ^RC
W_K
Data Byte
1010
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
S
T
Device
Type
A Address
R
T
Read/Write
1= Read
Slave Address
S
T
O
Lack of ACK (low) _P
from Master
determines last
data byte to be read
Master sends Read
request to Slave
Master Transmitter
to
Slave Receiver
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Shading Denotes
24042/43
SDA Output Active
2011 ILL 10 1.0
FIGURE 7. CURRENT ADDRESS BYTE READ MODE
SUMMIT MICROELECTRONICS, Inc.
6