SMB110 Datasheet, PDF (5/34 Pages) Summit Microelectronics, Inc. – Five Channel Programmable DC-DC System Power Manager

INTERNAL BLOCK DIAGRAM
COMP2_CH[2,3]
VM_CH[2,3]
100k
z
–
z
+ ^OA
z
CLAMP
COMP1_CH[2,3]
VREF
DIGITAL TO
ANALOG
CONVERTER
COMP2_CH1
VDD_CAP
z
z
+
–
LEVEL
SHIFTER
+
–
VREF
–
OA
z
z ++
CLAMP
COMP1_CH1
I²C/SMBUS
SDA
SCL
z
z
+
–
LEVEL
SHIFTER
+
VREF
–
z
–
OA
z
z+
CLAMP
z
–
+
LEVEL
SHIFTER
–
VREF
+
+
DUTY
–
CYCLE
LIMIT
MAX LIMIT
OSC
Fixed 800kHzLOW _LIMIT
GLITCH
FILTER
OVER VOLTAGE
DETECTION
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
+
DUTY
CYCLE
–
LIMIT
MAX LIMIT
OSC
Fixed 800kHz LOW LIMIT
GLITCH
FILTER
OVER VOLTAGE
DETECTION
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
+
DUTY
–
CYCLE
LIMIT
MAX LIMIT
OSC
Fixed 800kHz LOW LIMIT
GLITCH
FILTER
OVER VOLTAGE
DETECTION
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
VBATT
z
VDD_CAP 2.5V
REGULATOR
z
z
LDO
BANDGAP _VREF
z
z+
UV2 _z
–
zD Q
nBATT_FAULT
LEVEL
SHIFTER
+
UV1
–
SMB110
Preliminary Information
Channel 2 and 3
Synchronous buck
PWM Converter
HVSUP[2,3]
HSDRV[2,3]
DEADTIME
LSDRV[2,3]
SEQUENCING
LOGIC
ENABLE
ENABLE
ENABLE
z
100u
COMP
+
–
0.2 V
PWREN0
Channel 1
boost
PWM Converter
with Shutoff
PCHSEQ_CH1
LSDRV1
DRIVER
Channel 0
Negative
PWM Converter
LSDRV0
DRIVER
COMP1_CH0
COMP2_CH0
LEVEL
SHIFTER
VREF_OUT
X2
VREF
LDO_SUPPLY
Channel 5
Standby Series-Pass LDO
VSTANDBY
GND
Summit Microelectronics, Inc
2099 2.3 3/1/2005
5