S93WD662 Datasheet, PDF (3/14 Pages) Summit Microelectronics, Inc. – Precision Supply-Voltage Monitor and Reset Controller With a Watchdog Timer and 4k-bit Microwire Memory

S93WD662/S93WD663
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. See the
Applications Aid section for detailed use of the ready
busy status.
The format for all instructions is: one start bit; two op
code bits and either eight (x16) or nine (x8) address or
instruction bits.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93WD662/
WD663 will come out of the high impedance state and,
will first output an initial dummy zero bit, then begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay
(t_PD0 or t_PD1).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (t_CSMIN). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93WD662/WD663 can be determined by
selecting the device and polling the DO pin.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of 250ns (t_CSMIN). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93WD662/WD663 can be
tSKHI
t _SKLOW
t _CSH
SK
t _DIS
DI
VALID
tCSS
CS
VALID
tDIH
t _DIS
tPD0,t _PD1
tCSMIN
DO
DATA V ALID
Figure 1. Sychronous Data Timing
2013 ILL 3 1.0
SK
CS
AN AN_–1
A0
DI
11
0
tCS
STANDBY
HIGH-Z
tPD0
DO
0
tHZ
HIGH-Z
DN DN_–1
D1 D0
Figure 2. Read Instruction Timing
2013 ILL4 1.0
2013 2.1 8/2/00
3