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SMM665B Datasheet, PDF (18/30 Pages) Summit Microelectronics, Inc. – Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer
APPLICATIONS INFORMATION (CONTINUED)
RESTART OF POWER-ON CASCADE
SEQUENCING
Once a Force Shutdown or Power-off operation has
completed, the SMM665B can restart the Power-on
cascade sequencing. The device can be programmed
to automatically restart after a Force Shutdown
provided the PWR_ON/OFF pin remains in the active
state or the I2C Power-on command remains in the
command register. If this option is not selected, the
SMM665B requires toggling of the PWR_ON/OFF pin
or toggling of the I2C commands by issuing a Power-
off command and then reissuing the Power-on
command in order to restart Power-on sequencing.
In either case, assertion of the FS pin will prevent the
SMM665B from restarting Power-on sequencing. In
addition, the device can be programmed to check that
VDD and the 12VIN are within their programmed
voltage thresholds before restarting Power-on
sequencing.
In cases where brownout conditions (Figure 10) or
loss of power are used to cause a sequence off of the
supplies or a Force Shutdown, it is best to toggle the
PWR_ON/OFF pin or use the I2C Power commands
SMM665B
Preliminary Information
after the brownout condition is over or if the supplies
do not fully discharge before initiating a Power-on
sequence.
Recommended Use of the PWR_ON/OFF pin:
The PWR_ON/OFF pin is edge-triggered to lock out
false or nuisance signals during both the power-on
and power-off sequences. If during a system power-
down, whether deliberate or due to a failed power
system, the VDD_CAP voltage falls below 2.5V, the
SMM665B internal UVLO (UnderVoltage LockOut)
circuit resets all internal logic. Once power has
recovered above 2.6V the SMM665B will restart
assuming the PWR_ON/OFF pin is in the asserted
state or an I2C power command is issued. The
SMM665B can be used with the PWR_ON/OFF pin
either toggled by a logic level, controlled by a software
command or tied either high or low as described in the
data sheet.
VDD_CAP
3.6V, 5.5V
2.5V
2.6V
UVLO
(Internal)
Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’
Summit Microelectronics, Inc
2089 1.1 10/20/04
18