SMH4802 Datasheet, PDF (15/20 Pages) Summit Microelectronics, Inc. – Programmable -48V Hot-Swap Controller with Forced Shut Down

SMH4802
Preliminary Information
PROGRAMMING INFORMATION
I²C Bus Interface
The I²C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are:
a serial data line (SDA) and a serial clock line (SCL). The
SMH4802 supports a 100 kHz clock rate.
The SDA line must be connected to a positive supply by
a pull-up resistor located on the bus. The SMH4802
contains a Schmitt input on both the SDA and SCL signals.
Start and Stop Conditions
Both the SDA and SCL pins remain high when the bus is
not busy. Data transfers between devices may be
initiated with a Start condition only when SCL and SDA are
high. A high-to-low transition of the SDA while the SCL
pin is high is defined as a Start condition. A low-to-high
transition on SDA while SCL is high is defined as a Stop
condition. Figure 11 shows a timing diagram of the start
and stop conditions.
SCL
START
Condition
STOP
Condition
SCL
1
2
3
8
9
SDA
Trans
SDA
Rec
ACK
2062 Fig12
Figure 12. Acknowledge Timing
Read and Write
The first byte from a Master is always made up of a 7-bit
Slave address and the Read/Write (R/W) bit. The R/W bit
tells the Slave whether the Master is reading data from the
bus or writing data to the bus (1 = Read, 0 = Write). The
first four of the seven address bits are called the Device
Type Identifier (DTI). The DTI for the SMH4802 is
1010_BIN. The next three bits are Address values for A2,
A1, and A0 (if multiple devices are used). The SMH4802
issues an Acknowledge after recognizing a Start condi-
tion and its DTI. Figure 13 shows an example of a typical
master address byte transmission.
SCL
1
2
3
4
5
6
7
8
9
SDA In
SDA
1
0
1
0
x
x
x
R/W ACK
2062 Fig13
2062 Fig11
Figure 11. Start and Stop Conditions
Master/Slave Protocol
The master/slave protocol defines any device that sends
data onto the bus as a transmitter, and any device that
receives data as a receiver. The device controlling data
transmission is called the Master, and the controlled
device is called the Slave. In all cases the SMH4802 is
referred to as a Slave device since it never initiates any
data transfers.
Acknowledge
Data is always transferred in bytes. Acknowledge (ACK)
is used to indicate a successful data transfer. The
transmitting device releases the bus after transmitting
eight bits. During the ninth clock cycle the Receiver pulls
the SDA line low to acknowledge that it received the eight
bits of data. This is shown by the ACK in Figure 12.
When the last byte has been transferred to the Master
during a read of the SMH4802 the Master leaves SDA high
for a Not Acknowledge (NACK) cycle. This causes the
SMH4802 part to stop sending data, and the Master
issues a Stop on the clock pulse following the NACK.
Figure 13. Typical Master Address Byte Transmis-
sion
During a read by the Master device the SMH4802 trans-
mits eight bits of data, then releases the SDA line, and
monitors the line for an Acknowledge signal. If an
Acknowledge is detected, and no Stop condition is
generated by the Master, the SMH4802 continues to
transmit data. If an Acknowledge is not detected (NACK)
the SMH4802 terminates any subsequent data transmis-
sion. The read transfer protocol on SDA is shown in
Figure 14.
During a Master write the SMH4802 receives eight bits of
data, then generates an Acknowledge signal. The device
continues to generate the ACK condition on SDA until a
Stop condition is generated by the Master. The write
transfer protocol on SDA is shown in Figure 15.
Random Access Read
Random address read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a Write command which includes the Start condi-
tion and the Slave address field (with the R/W bit set to
Write) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
SMH4802 to the desired address.
SUMMIT MICROELECTRONICS, Inc.
2062 2.3 6/19/03
15