STM32F103ZDT6 Datasheet, PDF (98/130 Pages) STMicroelectronics – High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Table 54. I²S characteristics
Symbol
Parameter
Conditions
DuCy(SCK)
I2S slave input clock duty
cycle
f_CK
1/t_c(CK)
I²S clock frequency
Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
Slave mode
t_r(CK)
t_f(CK)
t_v(WS) ⁽¹⁾
I²S clock rise and fall time
WS valid time
t_h(WS) ⁽¹⁾
WS hold time
t_su(WS) ⁽¹⁾
t_h(WS) ⁽¹⁾
t_w(CKH) ⁽¹⁾
t_w(CKL) ⁽¹⁾
WS setup time
WS hold time
CK high and low time
t_{su(SD_MR)} ⁽¹⁾ Data input setup time
t_{su(SD_SR)} ⁽¹⁾
t_{h(SD_MR)(1)(2)}
t_{h(SD_SR)} ⁽¹⁾⁽²⁾
Data input setup time
Data input hold time
t_{v(SD_ST)} ⁽¹⁾⁽²⁾ Data output valid time
Capacitive load C_L = 50 pF
Master mode
Master mode
Slave mode
Slave mode
I2S2
I2S3
Master f_PCLK= 16 MHz, audio
frequency = 48 kHz
Master receiver
I2S2
I2S3
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable
edge)
t_{h(SD_ST)} ⁽¹⁾
Data output hold time
Slave transmitter (after enable
edge)
t_{v(SD_MT)} ⁽¹⁾⁽²⁾ Data output valid time
Master transmitter (after enable
edge)
t_{h(SD_MT)} ⁽¹⁾ Data output hold time
Master transmitter (after enable
edge)
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f_PCLK. For example, if f_PCLK=8 MHz, then T_PCLK = 1/f_PLCLK =125 ns.
Min
30
1.522
0
3
2
0
4
0
312.5
345
2
6.5
1.5
0
0.5
11
0
Max
Unit
70
%
1.525
6.5
8
MHz
ns
18
3
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Doc ID 14611 Rev 8