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| ST72104G Datasheet, PDF (97/135 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES | |||
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ST72104G, ST72215G, ST72216G, ST72254G
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as âabsolute maxi-
mum ratingsâ may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
13.2.1 Voltage Characteristics
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Symbol
Ratings
VDD - VSS
VIN
VESD(HBM)
VESD(MM)
Supply voltage
Input voltage on any pin 1) & 2)
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
13.2.2 Current Characteristics
Maximum value
Unit
6.5
V
VSS-0.3 to VDD+0.3
see Section 13.7.2 âAbsolute Elec-
trical Sensitivityâ on page 110
Symbol
IVDD
IVSS
Ratings
Maximum value
Unit
Total current into VDD power lines (source) 3)
80
Total current out of VSS ground lines (sink) 3)
80
Output current sunk by any standard I/O and control pin
25
IIO
Output current sunk by any high sink I/O pin
50
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
- 25
mA
±5
IINJ(PIN) 2) & 4)
Injected current on RESET pin
Injected current on OSC1 and OSC2 pins
±5
±5
Injected current on any other pin 5) & 6)
±5
ΣIINJ(PIN) 2)
Total injected current (sum of all I/O and control pins) 5)
± 20
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
TJ
Maximum junction temperature
(see Section 14.2 âTHERMAL CHARACTERISTICSâ on page 127 )
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k⦠for
RESET, 10k⦠for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
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