VL6624 Datasheet, PDF (94/106 Pages) STMicroelectronics – 1.3 Megapixel single-chip camera module

Electrical characteristics
VL6624/VS6624
13.7
Parallel data interface timing
VL6624/VS6624 contains a parallel data output port (D[7:0]) and associated qualification
signals (HSYNC, VSYNC, PCLK and FSO).
This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or
bit-serial output configurations. The port is disabled (high impedance) upon reset.
Figure 36. Parallel data output video timing
1/f_PCLK
t_PCLKL
t_PCLKH
PCLK
polarity = 0
D[0:7]
HSYNC,
VSYNC
t_DV
Valid
Table 51. Parallel data interface timings
Symbol
Description
Min.
f_PCLK
t_PCLKL
t_PCLKH
t_DV
PCLK frequency
PCLK low width
PCLK high width
PCLK to output valid
[1/2*(1/f_PCLK)] - 3.9
[1/2*(1/f_PCLK)] - 3.9
-5.15
Max.
54
[1/2*(1/f_PCLK)] + 3.9
[1/2*(1/f_PCLK)] + 3.9
1.62
Unit
MHz
ns
ns
ns
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