SPC564B74L7 Datasheet, PDF (93/118 Pages) STMicroelectronics – 32-bit MCU family built on the Power Architecture® for automotive body electronics applications

SPC564Bxx - SPC56ECxx
Electrical Characteristics
exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency
in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74
Reference Manual for details of this option and how to enable it.
Table 46. MII transmit signal timing⁽¹⁾
Spec
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0],
TX_EN, TX_ER invalid
M6
TX_CLK to TXD[3:0],
TX_EN, TX_ER valid
M7
TX_CLK pulse width high
M8
TX_CLK pulse width low
1. Output pads configured with SRE = 0b11.
5
—
35%
35%
—
25
65%
65%
ns
ns
TX_CLK period
TX_CLK period
Figure 22. MII transmit signal timing diagram
M7
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M8
M6
4.18.3 MII Async Inputs Signal Timing (CRS and COL)
Table 47. MII Async Inputs Signal Timing⁽¹⁾
Spec
Characteristic
Min
Max
M9
CRS, COL minimum pulse width
1.5
—
1. Output pads configured with SRE = 0b11.
Figure 23. MII async inputs timing diagram
CRS, COL
M9
Unit
TX_CLK period
Doc ID 17478 Rev 4
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