M24LR04E-R Datasheet, PDF (93/142 Pages) STMicroelectronics – 4-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz

M24LR04E-R
Command codes
Figure 61. Write AFI frame exchange between VCD and M24LR04E-R
VCD
SOF
Write AFI
request
EOF
M24LR04E-R
<-t₁-> SOF
Write AFI
response
EOF
Write sequence
when error
M24LR04E-R
<------------------ W_t -------------->
SOF
Write AFI
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write AFI command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write AFI command to the
beginning of the M24LR04E-R response).
26.9
Lock AFI
On receiving the Lock AFI request, the M24LR04E-R locks the AFI value permanently. The
Option_flag is supported.
During the RF write cycle W_t, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not Lock correctly the AFI value in memory. The W_t time is
equal to t_1nom + 18 × 302 µs.
Table 60. Lock AFI request format
Request Request_ Lock
SOF
flags
AFI
8 bits
28h
1. Gray means that the field is optional.
UID⁽¹⁾
64 bits
CRC16
16 bits
Request
EOF
Request parameter:
● Request Flags
● UID (optional)
Table 61. Lock AFI response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
● No parameter
Doc ID 022208 Rev 5
93/142