STM32L162XE Datasheet, PDF (92/129 Pages) STMicroelectronics – Ultra-low-power platform

Electrical characteristics
STM32L162xE
6.3.16
Communications interfaces
I²C interface characteristics
The device I²C interface meets the requirements of the standard I²C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and V_DD is
disabled, but is still present.
The I²C characteristics are described in Table 47. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output ction characteristics (SDA and SCL).
Table 47. I²C characteristics
Symbol
Parameter
Standard mode
I²C⁽¹⁾⁽²⁾
Min
Max
Fast mode I²C⁽¹⁾⁽²⁾
Min
Max
Unit
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA)
t_r(SCL)
t_f(SDA)
t_f(SCL)
t_h(STA)
t_su(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
4.7
-
1.3
4.0
-
0.6
250
-
100
-
3450⁽³⁾
-
-
1000
-
-
300
-
4.0
-
0.6
4.7
-
0.6
-
µs
-
-
900⁽³⁾
300
ns
300
-
µs
-
t_su(STO) Stop condition setup time
4.0
-
0.6
-
μs
t_w(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
C_b
Capacitive load for each bus
line
-
400
-
400
pF
Pulse width of spikes that
t_SP
are suppressed by the
0
50⁽⁴⁾
0
50⁽⁴⁾
ns
analog filter
1. Guaranteed by design.
2.
fa_{PcChLKie1vmeufsatsbt} emaotdleeaI²sCt
2 MHz to achieve standard mode
frequencies. It must be a multiple
I²C frequencies. It must be
of 10 MHz to reach the 400
at least 4 MHz
kHz maximum
to
I²C
fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above t_SP(max).
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