ST7MC1K2 Datasheet, PDF (90/371 Pages) STMicroelectronics – Clock, reset and supply management

On-chip peripherals
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure 33. Window watchdog timing diagram
T[5:0] CNT downcounter
WDGWR
3Fh
Refresh not allowed Refresh window
time
(step = 16384/f_OSC2)
T6 bit
t(s) _Reset
O_O^b_b^s_s^o_o^l_l^e_e^t_t^ee ^{PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucct(s) 10.1.6}
Low power modes
Table 34. Effect of low power modes on window watchdog
Mode
Description
Slow
No effect on watchdog. The downcounter continues to decrement at normal speed.
Wait
No effect on watchdog. The downcounter continues to decrement.
OIE bit in WDGHALT
MCCSR
bit in
register option byte
No watchdog reset is generated. The MCU enters Halt mode.
The watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
Halt
until the MCU receives an external interrupt or a reset.
0
0
If an interrupt is received (refer to Table 22: Interrupt mapping
to see interrupts which can occur in Halt mode), the watchdog
restarts counting after 256 or 4096 CPU clocks. If a reset is
generated, the watchdog is disabled (reset state) unless
hardware watchdog is selected by option byte. For application
recommendations see Section 10.1.8 below.
0
Active Halt
1
1
A reset is generated instead of entering Halt mode.
No reset is generated. The MCU enters Active Halt mode. The
watchdog counter is not decremented. It stops counting.
x
When the MCU receives an oscillator interrupt or external
interrupt, the watchdog restarts counting immediately. When
the MCU receives a reset the watchdog restarts counting after
256 or 4096 CPU clocks.
10.1.7
Hardware watchdog option
If Hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to Section 14.1: Flash option bytes.
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