STM32F101X6 Datasheet, PDF (9/64 Pages) STMicroelectronics – Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces

STM32F101xx
Description
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz.
Boot modes
At startup, boot pins are used to select one of five boot options:
● Boot from User Flash
● Boot from System Memory
● Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes
● V_DD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through V_DD pins.
● V_SSA, V_DDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL. In V_DD range (ADC is limited at 2.4 V).
● V_BAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V_DD is not present.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V_DD is below a specified threshold, V_POR/PDR, without the need for an
external reset circuit.
The device features an embedded Programmable voltage detector (PVD) that monitors the
V_DD power supply and compares it to the V_PVD threshold. An interrupt can be generated
when V_DD drops below the V_PVD and/or when V_DD is higher than the V_PVD threshold. The
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 9: Embedded reset and power control block characteristics for the values of
V_POR/PDR and V_PVD.
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