STCCP27A Datasheet, PDF (9/19 Pages) STMicroelectronics – 1.8V/2.8V High speed dual differential line receivers, Compact camera port decoder, I2C control line

STCCP27A
Electrical characteristics
Table 7.
Switching characteristics (R_T = 100Ω ± 1%, C_L = 10pF, over recommended
operating conditions unless otherwise noted. Typical values are referred to T_A =
25°C and V_DD = 2.8V, V_L = 1.8V)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
t_r
Rise time LVTTL Output voltage
(10% to 90%)
t_f
Fall time LVTTL output voltage
(90% to 10%)
t_{r I/O}
Rise time I²C input/output voltage
(20% to 80%)
t_{f I/O}
Fall time I²C input/output voltage
(80% to 20%)
t_pLH
Propagation delay time (CLK to V-
SYNC, H-SYNC) (low to high)
t_pHL
Propagation delay time (CLK to V-
SYNC, H-SYNC) (high to low)
t_pLH
Propagation delay time (CLK to
D1-D8) (low to high)
t_pHL
Propagation delay time (CLK to
D1-D8) (high to low)
Propagation delay time I²C
t_pLH input/output voltage (50% to 50%)
(Low to High)
Propagation delay time I²C
t_pHL input/output voltage (50% to 50%)
(High to Low)
t_EN
Enable delay time (EN to
V-SYNC, H-SYNC: t_PZL, t_PZH)
t_DIS
Disable delay time (EN to V-
SYNC, H-SYNC: t_PLZ, t_PHZ)
f_OPR Operating frequency
t_rEN = 2.0ns (10% to 90%)
t_fEN = 2.0ns (90% to 10%)
t_rEN = 2.0ns (10% to 90%)
t_fEN = 2.0ns (90% to 10%)
t_rD,CLK = 400ps (10% to 90%)
t_fD,CLK = 400ps (90% to 10%)
V_{CM D,CLK} = 0.9V, V_DD,CLK =
150mV
T_CLK Clock Period
Setup time (D to CLK) (low to high
t_SUD-CLK or high to low vs positive CLK
edge) (note 1) (see fig. 6)
t_HCLK-D
Hold time (CLK to D) (positive CLK
edge to D) (note 1) (see fig. 6)
3.1
4.0
ns
2.0
4.0
ns
320 ns
20
ns
6.5
8.5
ns
6.5
8.5
ns
6.5
8.5
ns
6.5
8.5
ns
100 ns
10
ns
20
µs
1000 ns
1
416 MHz
2.4
1000 ns
0.6
ns
1.0
ns
Note: 1 50% V_DIN to 50% V_DOUT
Symbol
Table 8. Capacitive characteristics
Test condition
Parameter
V_DD (V)
C_IN
Input Capacitance
(SYNC_SEL, EN)
2.65 to 3.6
V_L = 1.65V to 1.95V,
V_I = GND or V_DD
Value
T_A = 25°C
Unit
Min. Typ. Max.
3.5
pF
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