M28W320BT Datasheet, PDF (9/43 Pages) STMicroelectronics – 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory

M28W320BT, M28W320BB
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or data to be programmed during a Write Bus op-
eration.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V_ILand Reset is at V_IH the device is in active
mode. When Chip Enable is at V_IH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Write Protect (WP). Write Protect is an input to
protect or unprotect the two lockable parameter
blocks. When Write Protect is at V_IL, the lockable
blocks are protected and Program or Erase oper-
ations are not possible. When Write Protect is at
V_IH, the lockable blocks are unprotected and can
be programmed or erased (refer to Table 4, Mem-
ory Blocks Protection Truth).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V_IL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. When Reset is at V_IH, the device is in nor-
mal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
V_DD Supply Voltage. V_DD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V_DDQ Supply Voltage. V_DDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from V_DD. V_DDQ can be
tied to V_DD or can use a separate supply.
V_PP Program Supply Voltage. V_PP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V_DD and the
Program Supply Voltage V_PP can be applied in
any order.
If V_PP is kept in a low voltage range (0V to 3.6V)
V_PP is seen as a control input. In this case a volt-
age lower than V_PPLK gives an absolute protection
against program or erase, while V_PP > V_PP1 en-
ables these functions (see Table 11, DC Charac-
teristics for the relevant values). V_PP is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V_PP is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition V_PP must be
stable until the Program/Erase algorithm is com-
pleted (see Table 13 and 14).
V_SS Ground. V_SS is the reference for all voltage
measurements.
Note: Each device in a system should have
V_DD,V_DDQ and V_PP decoupled with a 0.1µF ca-
pacitor close to the pin. See Figure 7, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficient to carry the required V_PP
Program and Erase currents.
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