L6717A Datasheet, PDF (9/57 Pages) STMicroelectronics – Dynamic phase management

L6717A
Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 5. Pins connection (top view)
NB_UGATE
NB_PHASE
BOOT2
UGATE2
PHASE2
VCCDRV
NB_LGATE
LGATE2
LGATE1
PHASE1
UGATE1
BOOT1
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
L6717A
19
43
18
PAD (GND)
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
NB_CSN
NB_CSP
CS4N
CS4P
CS3N
CS3P
CS2N
CS2P
CS1N
CS1P
OSC / EN /FLT
ILIM
2.1
Pin descriptions
Pin#
1
2
3
4
Name
Table 2. Pin description
Function
PWROK
System-wide power good input (Ignored in PVI mode).
Internally pulled-low by 10μA. When low, the device will decode the two SVI bits SVC
and SVD to determine the Pre-PWROK Metal VID. When high, the device will actively
run the SVI protocol.
Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of
PWROK de-assertion. Latch is reset by VCC or EN cycle.
Device signal ground.
SGND
All the internal references are referred to this pin. Connect to the PCB signal ground.
VCC
Device power supply.
Operative voltage is 12 ±15%. Filter with 1μF MLCC to SGND.
COMP
CORE error amplifier output.
Connect with an R_F - C_F to FB.
The CORE section and/or the device cannot be disabled by grounding this pin.
DocID024465 Rev 1
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