ST72F521M Datasheet, PDF (89/199 Pages) STMicroelectronics – 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

ST72521M/R/AR
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.2 Main Features
s Full duplex synchronous transfers (on 3 lines)
s Simplex synchronous transfers (on 2 lines)
s Master or slave operation
s Six master mode frequencies (f_CPU/4 max.)
s f_CPU/2 max. slave mode frequency
s SS Management by software or hardware
s Programmable clock polarity and phase
s End of transfer interrupt flag
s Write collision, Master Mode Fault and Overrun
flags
10.5.3 General Description
Figure 53 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
Figure 53. Serial Peripheral Interface Block Diagram
SPIDR
Data/Address Bus
Read
Read Buffer
Interrupt
request
MOSI
MISO
SOD
bit
SCK
8-Bit Shift Register
Write
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SPI
STATE
CONTROL
SS ¹
0
MASTER
CONTROL
7
SPICR ⁰
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
SERIAL CLOCK
GENERATOR
SS
89/199