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STM32F100XC Datasheet, PDF (88/106 Pages) STMicroelectronics – Clock, reset and supply management
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Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
5.3.19 DAC electrical specifications
Symbol
Table 55. DAC characteristics
Parameter
Min Typ Max(1) Unit
Comments
VDDA
VREF+
VSSA
RLOAD(1)
Analog supply voltage
Reference supply voltage
Ground
Resistive load with buffer ON
2.4 -
2.4 -
0
-
5
-
RO(1)
Impedance output with buffer OFF
-
-
CLOAD(1)
Capacitive load
-
-
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
ON
0.2
-
DAC_OUT Higher DAC_OUT voltage with buffer
max(1)
ON
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
OFF
DAC_OUT Higher DAC_OUT voltage with buffer
max(1)
OFF
-
-
- 0.5
-
-
IDDVREF+
DAC DC current consumption in
quiescent mode (Standby mode)
-
-
IDDA
DAC DC current consumption in
quiescent mode (2)
-
-
-
-
3.6
V
3.6
V
0
V
- kΩ
15
kΩ
50
pF
-V
VDDA –
0.2
V
- mV
VREF+
– 1LSB
V
220 µA
380 µA
480 µA
-
VREF+ must always be below
VDDA
-
-
When the buffer is OFF, the
Minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 MΩ
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V
It gives the maximum output
excursion of the DAC.
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
With no load, middle code
(0x800) on the inputs
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
DNL(1)
INL(1)
-
Differential non linearity Difference
between two consecutive code-1LSB)
-
Integral non linearity (difference
between measured value at Code i
-
and the value at Code i on a line
drawn between Code 0 and last Code -
1023)
- ±0.5
- ±2
- ±1
- ±4
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
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