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STM32F303VCT6 Datasheet, PDF (87/132 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+48KB SRAM 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation
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STM32F302xx/STM32F303xx
Electrical characteristics
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL
compliant.
Table 52. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Low level input
voltage
VIH
High level input
voltage
Vhys
Schmitt trigger
hysteresis
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
0.3 VDD+0.07 (1)
-
- 0.475 VDD-0.2 (1)
-
-
0.3 VDD–0.3 (1)
-
-
0.445 VDD+0.398 (1) -
0.3 VDD (2)
V
-
0.5 VDD+0.2 (1)
-
-
0.2 VDD+0.95 (1)
-
-
0.7 VDD (2)
-
-
-
200 (1)
-
-
100 (1)
-
mV
-
300 (1)
-
TC, FT and FTf I/O
TTa I/O in digital mode
-
VSS ≤ VIN ≤ VDD
TTa I/O in digital mode
Ilkg
Input leakage
current (3)
VDD ≤ VIN ≤ VDDA
-
TTa I/O in analog mode
-
VSS ≤ VIN ≤ VDDA
FT and FTf I/O(4)
-
VDD ≤ VIN ≤ 5 V
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
25
-
±0.1
-
1
µA
-
±0.2
-
10
40
55
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
25
40
55
kΩ
CIO I/O pin capacitance
-
5
-
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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