ST92163 Datasheet, PDF (87/224 Pages) STMicroelectronics – 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

ST92163 - RESET AND CLOCK CONTROL UNIT (RCCU)
RESET/STOP MANAGER (Cont’d)
The on-chip Timer/Watchdog generates a reset
condition if the Watchdog mode is enabled
(WCR.WDEN cleared, R252 page 0), and if the
programmed period elapses without the specific
code (AAh, 55h) written to the appropriate register.
The input pin RESET is not driven low by the on-
chip reset generated by the Timer/Watchdog.
When the Reset pin goes high again, a delay of 10
ms occurs before exiting the Reset state (+-1
CLOCK1 period, depending on the delay between
the rising edge of the Reset pin and the first rising
edge of CLOCK1). Subsequently a short Boot rou-
tine is executed from the device internal Boot ROM,
and control then passes to the user program.
The Boot routine sets the device characteristics
and loads the correct values in the Memory Man-
agement Unit’s pointer registers, so that these
point to the physical memory areas as mapped in
the specific device. The precise duration of this
short Boot routine varies from device to device,
depending on the Boot ROM contents.
At the end of the Boot routine the Program Coun-
ter will be set to the location specified in the Reset
Vector located in the lowest two bytes of memory.
5.6.1 Reset Pin Timing
To improve the noise immunity of the device, the
Reset pin has a Schmitt trigger input circuit with
hysteresis. In addition, a filter will prevent an un-
wanted reset in case of a single glitch of less than
50 ns on the Reset pin. The device is certain to re-
set if a negative pulse of more than 20µs is ap-
plied. When the reset pin goes high again, a delay
of up to 4µs (at 8 MHz.) will elapse before the
RCCU detects this rising front. From this event on,
79870 (about 10 ms at 8 MHz.) oscillator clock cy-
cles (CLOCK1) are counted before exiting the Re-
set state (+-1 CLOCK1 period depending on the
delay between the positive edge the RCCU de-
tects and the first rising edge of CLOCK1)
If the ST9 is a ROMLESS version, without on-chip
program memory, the memory interface ports are
set to external memory mode (i.e Alternate Func-
tion) and the memory accesses are made to exter-
nal Program memory with wait cycles insertion.
Figure 46. Recommended Signal to be Applied
on Reset Pin
V_RESET
V_CC
0.7 V_CC
0.3 V_CC
20 µs
Minimum
5.7 STOP MODE
In Stop mode, the Reset/Stop Manager can also
stop all oscillators without resetting the device.
For information on entering and exiting Stop
Mode, refer to the Wake-Up/Interrupt lines man-
agement unit (WUIMU) chapter. In Stop Mode, all
context information is preserved and the internal
clock is frozen in the high state.
On exiting Stop mode, the MCU resumes execu-
tion of the user program after a delay of 255
CLOCK2 periods, an interrupt is generated and
the EX_STP bit in CLK_FLAG is set.
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