ST7262XXX Datasheet, PDF (86/139 Pages) STMicroelectronics – Low speed USB 8-bit MCU with 3 endpoints

ST7262xxx
USB INTERFACE (Cont’d)
Bit 3 = IOVR Interrupt overrun.
This bit is set when hardware tries to set ERR, or
SOF before they have been cleared by software.
0: No overrun detected
1: Overrun detected
of each bit, please refer to the corresponding bit
description in ISTR.
CONTROL REGISTER (CTLR)
Read / Write
Bit 2 = ESUSP End suspend mode.
Reset Value: 0000 0110 (06h)
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
7
0
terface up from suspend mode.
This interrupt is serviced by a specific vector, in or-
) der to wake up the ST7 from HALT mode.
t(s ^{0: No End Suspend detected}
1: End Suspend detected
duc _{Bit 1 = RESET USB reset.}
ro ^{This bit is set by hardware when the USB reset se-}
P ^{quence is detected on the bus.}
0: No USB reset signal detected
te 1: USB reset signal detected
le _{Note: The DADDR, EP0RA, EP0RB, EP1RA,}
o _{EP1RB, EP2RA and EP2RB registers are reset by}
s _{a USB reset.}
- ^Ob Bit 0 = SOF Start of frame.
) This bit is set by hardware when a low-speed SOF
t(s ^{indication (keep-alive strobe) is seen on the USB}
bus. It is also issued at the end of a resume se-
c _quence.
u _{0: No SOF signal detected}
d _{1: SOF signal detected}
ro _{Note: To avoid spurious clearing of some bits, it is}
P _{recommended to clear them using a load instruc-}
te ^{tion where all bits which must not be altered are}
le ^{set, and all bits to be cleared are reset. Avoid read-}
modify-write instructions like AND, XOR..
Obso ^{INTERRUPT MASK REGISTER (IMR)}
0 0 0 0 RESUME PDWN FSUSP FRES
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be halted allowing at least
600 ns before issuing the HALT instruction.
0: Suspend mode inactive
1: Suspend mode active
Read / Write
When the hardware detects USB activity, it resets
Reset Value: 0000 0000 (00h)
this bit (it can also be reset by software).
7
0
SUS DOV CTR ERR IOVR ESU RES SOF
PM RM M
M
M SPM ETM M
Bits 7:0 = These bits are mask bits for all interrupt
condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit
is set, and the I bit in the CC register is cleared, an
interrupt request is generated. For an explanation
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
86/139
Doc ID 6996 Rev 5