ST10F272M Datasheet, PDF (86/175 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

System reset
ST10F272M
Figure 21. Synchronous short / long hardware RESET (EA = 1)
≤4 TCL⁽⁴⁾ ≤12 TCL
< 1032 TCL
RSTIN
(1)
≥ 50ns
≤ 500ns
RSTF
(After Filter)
P0[15:13]
(3)
≥ 50ns
≤ 500ns
≥ 50ns
≤ 500ns
not transparent
≤ 2 TCL
P0[12:2]
not t.
transparent
not t.
P0[1:0]
IBUS-CS
(Internal)
FLARST
RST
RSTOUT
not transparent
≤ 1ms
1024 TCL
8 TCL
not t.
7 TCL
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
RPD
200µA Discharge
(2) _{VRPD > 2.5V Asynchronous Reset not entered}
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for
5V operation), the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit
BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked
by the internal filter (refer to Section 21.1)
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