USBLC6-2 Datasheet, PDF (8/11 Pages) STMicroelectronics – VERY LOW CAPACITANCE ESD PROTECTION

USBLC6-2
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-2 cell. In this model, the diodes are defined by the
PSPICE parameters given in figure 17.
Figure 16: PSPICE model
D+in
GND
D-in
LI/O
LGND
LI/O
RI/O
RGND
MODEL = Dlow
MODEL = Dhigh
MODEL = Dzener
RI/O
MODEL = Dlow
MODEL = Dhigh
RI/O
LI/O
RI/O
LI/O
RI/O
LI/O
D+out
VBUS
D-out
Note: This simulation model is available only for an ambient temperature of 27°C.
Figure 17: PSPICE parameters
Figure 18: USBLC6-2 PCB layout
considerations
Dlow
Dhigh
Dzener
LI/O
750p
BV
50
50
7.3
RI/O
110m
CJ0
0.9p
2.0p
40p
LGND 550p
IBV
1m
1m
1m
RGND 60m
M
0.3333 0.3333 0.3333
RS
0.2
0.52
0.84
VJ
0.6
0.6
0.6
TT
0.1u
0.1u
0.1u
D+in
GND
D-in
1
USBLC6-2
D+out
VBUS
CBUS = 100nF
D-out
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