STM6315 Datasheet, PDF (8/21 Pages) STMicroelectronics – Open Drain Microprocessor Reset

Operation
STM6315
2.4
Valid RST Output Down to V_CC = 0V
When V_CC falls below 1V, the RST output no longer sinks current, but becomes an open
circuit. In most systems this is not a problem, as most MCUs do not operate below 1V.
However, in applications where RST output must be valid down to 0V, a pull-down resistor
may be added to hold the RST output low. This resistor must be large enough to not load the
RST output, and still be small enough to pull the output to Ground. A 100KΩ resistor is
recommended.
Figure 5. Reset Timing Diagram
VCC
VRST
RST ^{VCC (min)}
trec
AI11166
Figure 6. Manual Reset Timing Diagram, Switch Bounce/Debounce
MR Glitch Rejection
MR
RST
MR Input Pulse Width
trec
MR-to-RST Delay
AI11167b
8/21