STE100P_06 Datasheet, PDF (8/31 Pages) STMicroelectronics – 10/100 FAST ETHERNET 3.3V TRANSCEIVER

STE100P
6 REGISTERS AND DESCRIPTORS DESCRIPTION
There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which
are defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and
clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of
IEEE802.3u standard.
In addition, there are 4 special registers for advanced chip control and status information.
6.1 Register List
Table 4. Register List
Address
Reg. Index
0
PR0
1
PR1
2
PR2
3
PR3
4
PR4
5
PR5
6
PR6
17
PR17
18
PR18
19
PR19
20
PR20
Name
XCR
XSR
PID1
PID2
ANA
ANLPA
ANE
XCIIS
XIE
100CTR
XMC
Register Descriptions
XCVR Control Register
XCVR Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
XCVR Configuration Information and Interrupt Status Register
XCVR Interrupt Enable Register
100Base-TX PHY Control/Status Register
XCVR Mode Control Register
6.2 Register Descriptions
Table 5. Register Descriptions
Bit #
Name
Descriptions
Default Val RW Type
PR0- XCR, XCVR Control Register. The default values on power-up/reset are as listed below.
15
XRST Reset control.
0
R/W
1: Device will be reset. This bit will be cleared by STE100P
itself after the reset is completed.
14
XLBEN Loop-back mode select.
1: Loop-back mode is selected.
0: Normal mode
0
R/W
13
SPSEL Network Speed select. This bit’s selection will be ignored if
1
R/W
Auto-Negotiation is enabled(bit 12 of PR0 = 1).
1:100Mbps is selected.
0:10Mbps is selected.
12
ANEN Auto-Negotiation ability control.
1: Auto-Negotiation function is enabled.
0: Auto-Negotiation is disabled.
1
R/W
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