STA2064 Datasheet, PDF (8/19 Pages) STMicroelectronics – Cartesio™ family infotainment application processor with embedded GPS

System description
STA2064
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
Communication interfaces
USB
STA2064 embeds one USB2.0 OTG high-speed interface, featuring:
a) High-speed signalling rate at 480 Mbit/s
b) Support for full-speed (12 Mbit/s) signaling bit rate
c) Support for session request protocol (SRP) and host negotiation protocol (HNP)
d) Up to 7 bidirectional endpoints plus control endpoint 0
e) 8192 bytes maximum FIFO dimension
f) Dynamic FIFO allocation
To reduce total system cost, it is equipped with a built-in USB 2.0 PHY.
With the goal of reducing the BOM cost for the customer, the USB 2.0 PHY also supports
this additional muxing scheme:
● the USB D- wire is used as either the USB D- signal or UART receive data signal
● the USB D+ wire is used as either the USB D+ signal or the UART transmit data signal
UART
STA2064 features three Autobaud UARTs. One offers all modem control/status signals.
They are enhanced version of the industry-standard 16C550 UART.
I²C
The I²C controller is an interface designed to support the physical and data link layer
according to I²C standard revision 2.1 (January 2000). The I²C bus is a 2-wire serial bus
that provides a low-cost interconnection between ICs. STA2064 features three I²C
interfaces.
MSP
The multichannel serial port (MSP) is a synchronous receive and transmit serial interface.
STA2064 features three MSPs.
SSP
STA2064 features two SSPs up to 24Mbit/sec for synchronous serial communication with
external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with
programmable word length up to 32 bits.
SPDIF
This interface takes SPDIF as input and extracts data and other channel information
encrypted in SPDIF Frame format as per IEC958 standards. Data can be transferred to
memory, using DMA support, or directly to C3 decoder without CPU intervent. SPDIF block
supports up to 2X data streams.
8/19
Doc ID 16057 Rev 1