SA555DT Datasheet, PDF (8/20 Pages) STMicroelectronics – General-purpose single bipolar timers

Application information
4
Application information
NE555 - SA555 - SE555
4.1
Monostable operation
In the monostable mode, the timer generates a single pulse. As shown in Figure 12, the
external capacitor is initially held discharged by a transistor inside the timer.
Figure 12. Typical schematics in monostable operation
V_CC = 5 to 15V
Reset
R1
4
8
Trigger
2
7
NE555 6
C1
Output
3
Control Voltage
5
1
0.01μF
The circuit triggers on a negative-going input signal when the level reaches 1/3 V_CC. Once
triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R₁C₁ and
is easily determined by Figure 14.
Note that because the charge rate and the threshold level of the comparator are both
directly proportional to supply voltage, the timing interval is independent of supply. Applying
a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2)
during the timing cycle discharges the external capacitor and causes the cycle to start over.
The timing cycle now starts on the positive edge of the reset pulse. During the time the reset
pulse is applied, the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short-
circuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time constant t = R₁C₁. When the voltage across
the capacitor equals 2/3 V_CC, the comparator resets the flip-flop which then discharges the
capacitor rapidly and drives the output to its LOW state.
Figure 13 shows the actual waveforms generated in this mode of operation.
When Reset is not used, it should be tied high to avoid any possibility of unwanted
triggering.
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Doc ID 2182 Rev 6