M48Z35_11 Datasheet, PDF (8/24 Pages) STMicroelectronics – 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM

Operating modes
2
Operating modes
M48Z35, M48Z35Y
Note:
2.1
The M48Z35/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V_CC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V_CC. As V_CC falls below
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2. Operating modes
Mode
V_CC
E
G
W DQ0-DQ7
Deselect
WRITE
READ
4.75 to 5.5 V
or
4.5 to 5.5 V
V_IH
X
X
V_IL
X
V_IL
V_IL
V_IL
V_IH
READ
V_IL
V_IH
V_IH
Deselect V_SO to V_PFD (min)⁽¹⁾
X
X
X
Deselect
≤ V_SO(1)
X
X
X
1. See Table 6 on page 12 for details.
High Z
D_IN
D_OUT
High Z
High Z
High Z
X = V_IH or V_IL; V_SO = Battery backup switchover voltage.
Power
Standby
Active
Active
Active
CMOS standby
Battery backup mode
READ mode
The M48Z35/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable) is
low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 address
inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the data I/O pins within address access time (t_AVQV) after the last address input
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the chip enable
access time (t_ELQV) or output enable access time (t_GLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t_AVQV, the data lines will be driven to an indeterminate state until t_AVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t_AXQX) but will go indeterminate until the next address access.
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