M48T559Y Datasheet, PDF (8/18 Pages) STMicroelectronics – 64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED

M48T559Y
Table 10. Register Map
Data
Address
D7
D6
D5
D4
D3
D2
D1
D0
Function/Range
BCD Format
1FFFh
10 Years
Year
Year
00-99
1FFEh
0
0
0
10 M
Month
Month
01-12
1FFDh
0
0
10 Date
Date
Date
01-31
1FFCh
0
FT
0
0
0
Day
Day
01-07
1FFBh
0
0
10 Hours
Hours
Hour
00-23
1FFAh
0
10 Minutes
Minutes
Minutes
00-59
1FF9h
ST
10 Seconds
Seconds
Seconds
00-59
1FF8h
W
R
S
Calibration
Control
1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0
Watchdog
1FF6h AFE
Y
ABE
Y
Y
Y
Y
Y
Interrupts
1FF5h RPT4 Y
Al. 10 Date
Alarm Date
Alarm Date
01-31
1FF4h RPT3 Y
Al. 10 Hours
Alarm Hours
Alarm Hours
00-23
1FF3h RPT2
Alarm 10 Minutes
Alarm Minutes
Alarm Minutes
00-59
1FF2h RPT1
Alarm 10 Seconds
Alarm Seconds
Alarm Seconds
00-59
1FF1h
Y
Y
Y
Y
Y
Y
Y
Y
Unused
1FF0h WDF AF
Z
BL
Z
Z
Z
Z
Flags
Keys:
S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
Z = ’0’ and are Read only
AF = Alarm Flag
The M48T559Y may respond to transient noise
spikes on V_CC that reach into the deselect window
during the time the device is sampling V_CC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When V_CC drops below V_SO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T559Y for
an accumulated period of at least 7 years when
V_CC is less than V_SO. As system power returns
and V_CC rises above V_SO, the battery is discon-
nected, and the power supply is switched to exter-
BL = Battery Low
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
nal V_CC. Write protection continues until V_CC
reaches V_PFD (max) plus t_REC. For more informa-
tion on Battery Storage Life refer to the Application
Note AN1012.
POWER-ON RESET
The M48T559Y continuously monitors V_CC. When
V_CC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on power-
up for 40ms to 200ms after V_CC passes V_PFD. An
external pull-up resistor to V_CC is required (1kΩ re-
sistor is recommended). The reset pulse remains
active with V_CC at V_SS.
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