M24128-DRE Datasheet, PDF (8/41 Pages) STMicroelectronics – 128-Kbit serial IC bus EEPROM - 105C operation

Signal description
2
Signal description
M24128-DRE
2.1
Serial Clock (SCL)
The signal applied on this input is used to strobe the data available on SDA(in) and to output
the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected between SDA and V_CC (Figure 10 and Figure 11
indicate how to calculate the value of the pull-up resistor).
2.3
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to V_CC or V_SS, as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0).
Figure 3. Device select code
6##
6##
-XXX
%I
-XXX
%I
633
633
!I
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
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