ST52T400 Datasheet, PDF (79/94 Pages) STMicroelectronics – 8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

ST52T400/T440/E440/T441
11.8 ESD Pin Protection Strategy
In order to protect an integrated circuit against
Electro-Static Discharge the stress must be
controlled to prevent degradation or destruction of
the circuit elements. Stress generally affects the
circuit elements, which are connected to the pads
but can also affect the internal devices when the
supply pads receive the stress. The elements that
are to be protected must not receive excessive
current, voltage, or heating within their structure.
An ESD network combines the different input and
output protections. This network works by allowing
safe discharge paths for the pins subject to ESD
stress. Two critical ESD stress cases are
presented in Figure 11.8 and Figure 11.9 for
standard pins.
11.8.1 Standard Pin Protection
In order to protect the output structure the following
elements are added:
- A diode to V_DD (3a) and a diode from V_SS (3b)
- A protection device between V_DD and V_SS (4)
In order protect the input structure the following
elements are added:
- A resistor in series with pad (1)
- A diode to V_DD (2a) and a diode from V_SS (2b)
- A protection device between V_DD and V_SS (4)
Figure 11.8 Safe discharge path subjected to ESD stress
VDD
Main path
Path to avoid
VSS
(3a)
(2a)
(1)
O UT (4) IN
(3b)
(2b)
Figure 11.9 Negative Stress on a Standard Pad vs. VDD
VDD
VSS
VDD
Main path
VSS
(3a)
(2a)
(1)
OUT (4) IN
(3b)
(2b)
VDD
VSS
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