PSD4XX Datasheet, PDF (79/123 Pages) STMicroelectronics – Low Cost Field Programmable Microcontroller Peripherals

PSD4XX Family
System
Configuration
(cont.)
12.1 Reset Input
The reset input to the PSD4XX (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in
reset during T2 range. (See Figure 48). The PSD4XX must be reset at power up before it
can be used.
12.2 ZPLD and Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
12.3 Register Values During and After Reset
Table 24 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
12.4 ZPLD Macrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
t A product term (.RE) defined by the user in PSDabel, or
t The MACRO-RST (Reset) input, enabled and defined in PSDabel.
Table 24. Registers Reset Values
Register Name
Device
Control
Port A, B, C, D, E
Data Out
(data or address)
Direction
Open Drain
Page Register
PMMR0, PMMR1
VM
Port A, B, C, D, E
Port A, B, C, D, E
Port C, D
Page Logic
Power Management Unit
Volatile Memory
Reset State
Set to “0”
(Address Out Mode)
Set to “0”
Set to “0” – Input Mode
Set to “0” – CMOS Outputs
Set to “0”
Set to “0”
Set to “0”
Table 25. I/O Pin Status During Reset and Standby Mode
Port Configuration
Port I/O
ZPLD Output
Address Out
Data Port
Peripheral I/O
Reset
Input
Active
Tri-stated
Tri-stated
Tri-stated
Stand-by Mode
Unchanged
Depend on Inputs to the ZPLD
Not Defined
Tri-stated
Tri-stated
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