PSD4256G6V Datasheet, PDF (73/100 Pages) STMicroelectronics – Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs

PSD4256G6V
Input Control Signals
The PSD provides the option to turn off the ad-
dress input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/
AS, PD0) and WRITE-Enable High-byte (WRH/
DBE, PD3)) to the PLD to save AC power con-
sumption. These signals are inputs to the PLD
Table 50. ADP Counter Operation
APD Enable Bit ALE PD Polarity
0
X
1
X
1
1
1
0
ALE Level
X
Pulsing
1
0
AND Array. During Power-down mode, or, if any of
them are not being used as part of the PLD logic
equation, these control signals should be disabled
to save AC power. They are disconnected from the
PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6
to a 1 in PMMR2.
APD Counter
Not Counting
Not Counting
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.