TDA7535013TR Datasheet, PDF (7/12 Pages) STMicroelectronics – Delta/sigma cascade 20 bit stereo DAC

TDA7535
3
I²S interface
I²S interface
Figure 3. I²S interface diagram
Left
FSYNC
Right
32 * SCK
32 * SCK
SCK
SDATA
20 Bits
20 Bits
uct(s) MSB
LSB
MSB
LSB
Prod _{Figure 4. I}²_{S timings}
lete ^SDATA
Valid
so _FSYNC
roduct(s) ^{- Ob SCK}
t_sckr
Valid
t_sckf
t_lrw- t_lrw+
t_sds
t_sckpl
t_sdh
t_sckph
t_sck
lete ^{P Table 10. Timing characteristics}
o _Timing
Description
Obs^{tsck Clock cycle(1)}
Min.
Max.
Unit
1/(64*Fs) - 150ps_RMS 1/(64*Fs) + 150ps_RMS ns
t_sckpl SCK phase low
0.5*t_sck - 1%
0.5*t_sck +1%
ns
t_sckph SCK phase high
0.5*t_sck - 1%
0.5*t_sck +1%
ns
t_lrw-
FSYNC switching time window before SCK falling
edge⁽²⁾
0
0.125*t_sck-10
ns
t_lrw+
FSYNC switching time window after SCK falling
edge⁽²⁾⁾
0
0.125*t_sck-10
ns
t_sds SDATA setup time
t_sdh SDATA hold time
60
ns
30
ns
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