TDA7478_11 Datasheet, PDF (7/11 Pages) STMicroelectronics – Single chip RDS demodulator

TDA7478
3
Output timing
Output timing
The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data.
According to the internal PLL lock condition data change can result on the falling or on the
rising clock edge. (see Figure 3). Whichever clock edge is used by the decoder (rising or
falling edge) the data will remain valid for 416.7 μs after the clock transition.
Figure 3. RDS timing diagram
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Doc 10679 Rev 3
7/11