TDA7309 Datasheet, PDF (7/12 Pages) STMicroelectronics – DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS

TDA7309
SDA, SCL I²CBUS TIMING
Symbol
f_SCL
t_BUF
t_HD:STA
t_{L OW}
t_HIGH
t_SU:STA
t_HD:DA
t_SU:DAT
t_R
t_F
t_SU:STO
Parameter
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I²C BUS master.
Min.
0
1.3
0.6
1.3
0.6
0.6
0.300
100
20
20
0.6
Typ.
Max. Unit
400
kHz
µs
µs
µs
µs
µs
µs
ns
300 ns (*)
300 ns (*)
µs
Definition of timing on the I²C-bus
SDA
t_BUF
t_R t_F
SCL
t_LOW
P
S ^tHD;STA
P = STOP
S = START
t_HD;DAT
t_HIGH
t_F
t_HD;STA
t_SP ^tSU;STO
t_SU;STA
t_SU;DAT
Sr
P
D95AU314
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