STV7697B Datasheet, PDF (7/18 Pages) STMicroelectronics – Scan Driver for Plasma Display Panels

STV7697B
2 Circuit Description
Figure 2: STV7697B Block Diagram
CLR
CLK
SIN (SOUT)
STB
BLK
POL
64-bit Shift Register
P1
P64
S1
Q1 Q2
Latch
S64
Q63 Q64
V_SSP1
STV7697B
V_PP1 V_SSP2
V_PP2
OUT1
OUT64
Circuit Description
F/R
SOUT
V_SSSUB
V_SSLOG
V_CC
V_SSP1
V_SSP2
V_PP1
V_PP2
The STV7697B includes all the necessary logic and power circuits to drive the rows of electrodes of
a plasma display panel (PDP). The state of the displayed line is loaded into the shift register. Data
is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented
at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade
several drivers to perform any vertical resolution (Table 5). Inputs CLK, STB, SIN and SOUT are
Schmitt trigger inputs.
Table 5: Shift Register Truth Table
F/R
CLK
SIN
SOUT
Comments
H
Rise
In
Out
Forward Shift
H
L or H
In
Out
Steady
L
Rise
Out
In
Reverse Shift
L
L or H
Out
In
Steady
The forward / reverse (F/R) input is used to select the direction of the shift register where data input/
output status is set according to the selected direction. In Reverse mode (F/R = low), data is input
on the SOUT pin and output on the SIN pin.
The maximum frequency of the shift clock is 8 MHz.
The clear signal (CLR) resets the shift register data to 0 when it is pulled to a high level.
Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the
latch input (STB) is at low level.
7/18