STEVAL-IME009V1 Datasheet, PDF (7/12 Pages) STMicroelectronics – Load simulator using signal equivalent circuits

STEVAL-IME009V1
Schematic diagrams
Figure 6. STEVAL-IME009V1 circuit schematic (6 of 9)
U4D
FPGA - Bank 3
IO_3_L01N_VREF
IO_3_L01P
N3
N4
P3
IO_3_L02N _P4
IO_3_L02P
IO_3_L31N_VREF
M5
L6
IO_3_L31P _U1
IO_3_L32N_M3DQ15
IO_3_L32P_M3DQ14
U2
T1
IO_3_L33N_M3DQ13
IO_3_L33P_M3DQ12
T2
P1
IO_3_L34N_M3UDQSN _P2
IO_3_L34P_M3UDQS _N1
IO_3_L35N_M3DQ11
IO_3_L35P_M3DQ10
N2
M1
IO_3_L36N_M3DQ9
IO_3_L36P_M3DQ8
IO_3_L37N_M3DQ1
M3
L1
L2
IO_3_L37P_M3DQ0
IO_3_L38N_M3DQ3
K1
K2
IO_3_L38P_M3DQ2 _L3
IO_3_L39N_M3LDQSN _L4
IO_3_L39P_M3LDQS _J1
IO_3_L40N_M3DQ7 _J3
IO_3_L40P_M3DQ6
IO_3_L41N_GCLK26_M3DQ5
H1
H2
IO_3_L41P_GCLK27_M3DQ4 _K3
IO_3_L42N_GCLK24_M3LDM
IO_3_L42P_GCLK25_TRDY2_M3UDM
K4
K5
IO_3_L43N_GCLK22_IRDY2_M3CASN _L5
IO_3_L43P_GCLK23_M3RASN
IO_3_L44N_GCLK20_M3A6
H3
H4
IO_3_L44P_GCLK21_M3A5 _K6
IO_3_L45N_M3ODT
IO_3_L45P_M3A3
L7
G1
IO_3_L46N_M3CLKN
IO_3_L46P_M3CLK
IO_3_L47N_M3A1
G3
J6
J7
IO_3_L47P_M3A0 _F1
IO_3_L48N_M3BA1 _F2
IO_3_L48P_M3BA0 _H5
IO_3_L49N_M3A2 _H6
IO_3_L49P_M3A7
IO_3_L50N_M3BA2
E1
E3
IO_3_L50P_M3WE
IO_3_L51N_M3A4
F3
F4
IO_3_L51P_M3A10 _D1
IO_3_L52N_M3A9
IO_3_L52P_M3A8
D2
G6
IO_3_L53N_M3A12 _H7
IO_3_L53P_M3CKE
IO_3_L54N_M3A11
IO_3_L54P_M3RESET
D3
E4
F5
IO_3_L55N_M3A14
IO_3_L55P_M3A13
F6
C1
IO_3_L83N_VREF _C2
IO_3_L83P
FPGA BANK 3
NOT USED
XC6SLX16-2CSG324C
GSPG01082014DI1355
DocID026792 Rev 1
7/12
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