M48T512Y Datasheet, PDF (7/21 Pages) STMicroelectronics – 3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM

M48T512Y, M48T512V*
READ Mode
The M48T512Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 19 Ad-
dress Inputs defines which one of the 524,288
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Ac-
cess Time (t_AVQV) after the last address input sig-
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access Times (t_ELQV) or Output
Enable Access Time (t_GLQV). The state of the eight
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t_AVQV, the
data lines will be driven to an indeterminate state
until t_AVQV. If the Address Inputs are changed
while E and G remain active, output data will re-
main valid for Output Data Hold Time (t_AXQX) but
will go indeterminate until the next Address Ac-
cess.
Figure 5. READ Mode AC Waveforms
A0-A18
E
G
DQ0-DQ7
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
Note: WE = High.
AI02389
Table 3. READ Mode AC Characteristics
M48T512Y
M48T512V
Symbol
Parameter⁽¹⁾
–70
–85
Min
Max
Min
Max
t_AVAV READ Cycle Time
70
85
t_AVQV Address Valid to Output Valid
70
85
t_ELQV Chip Enable Low to Output Valid
70
85
t_GLQV Output Enable Low to Output Valid
40
55
t_ELQX(2) Chip Enable Low to Output Transition
5
5
t_GLQX(2) Output Enable Low to Output Transition
5
5
t_EHQZ(2) Chip Enable High to Output Hi-Z
25
30
t_GHQZ(2) Output Enable High to Output Hi-Z
25
30
t_AXQX Address Transition to Output Transition
10
5
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. C_L = 5pF.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
7/21